This invention relates to the processing of semiconductor devices and circuits, and more particularly relates to a method for selectively treating surface features of a semiconductor structure above a predetermined vertical level.
As the semiconductor devices in integrated circuits become smaller and more closely packed, the upper layers of the devices, such as the metal interconnect patterns, must accommodate more abrupt changes in surface topography caused by the smaller lateral dimensions of the devices. Deviations from planarity, sometimes called "steps", make accurate micropatterning of the surface configuration difficult. In extreme cases, steps cannot be covered completely, so that discontinuities occur in the overlying metal layer. The problem is accentuated as more layers are added, such as in the case of interconnected multi-level integrated circuits, creating more complicated surface topographies having more and larger steps.
Etching techniques are known which will "planarize" a non-planar surface. For example, U.S. Pat. No. 4,025,411 describes a process in which the non-planar surface of a semiconductor device is made planar by first applying a layer of liquid photoresist over the uneven surface, then allowing the photoresist to solidify, and finally etching the surface by a physical etching method (for example, RF sputter etching or ion milling) which removes the photoresist and the underlying material at about the same rate. Another planarization technique involving physical etching is described in U.S. Pat. No. 4,510,173.
However, such physical etching techniques require the use of sophisticated equipment, which must be carefully controlled in order to achieve satisfactory results.
Chemical methods of planarization are also known. For example, U.S. Pat. No. 3,718,514, issued Feb. 17, 1973, describes a method for removing projections (having a height of from less than one to about fifty microns) from epitaxial layers such as silicon, the method comprising first forming an oxide layer on the surface, and then forming an etch-resistant film on the oxide layer, in a manner to form pin holes in the film. These pin holes have a high probability of occuring at the sites of the projections. The portions of the oxide layer thus exposed by the pin holes are removed by chemical etching, after which the film is stripped from the oxide layer. The projections exposed by the oxide etch are then removed by a chemical etchant selective for silicon. Due to the random nature in which the projections are exposed for etching, the above steps are preferably repeated one or more times in order to increase the effectiveness of the process.
An improvement to the above process is described in German Offenlegungsschrift No. 2431467, laid open Jan. 22, 1976, in which the surface of an epitaxial layer is coated directly with a film of an etch-resistant material. Typical etch-resistant materials said to be suitable for the practice of the invention include the photosensitive resists conventionally used in semicondcutor processing as well as suitable carbon derivatives such as picein. The film completely covers the smallest projections, while only covering the sides of the larger projections. The surface of the film is markedly uneven. Then, while the epitaxial surface is in a horizontal orientation, the film is heated to near the yield point of the material (for example, 50.degree. C. to 250.degree. C.) in order to allow it to flow, thereby planarizing the surface, sealing pin holes and liberating the projections from the coating.
In this condition, the layer has receded from the sides of the larger projections (up to 100 micrometers in height) and no longer covers the smaller projections. The projections thus exposed are subsequently removed by a chemical etchant.
While this process is simpler than the multistep process of U.S. Pat. No. 3,718,514, it would nevertheless be desirable to eliminate the need for a separate heating step to fluidize the etch-resistant material in order to selectively expose the projections for etching.
Accordingly, a principal object of the invention is to provide a single step, economical process for forming a continuous, substantially planar protective layer on the surface of a semiconductor structure to be treated.
Another object of the invention is to provide such a layer which surrounds projections from the surface of the structure so that the projections may be subsequently selectively treated.
Another object of the invention is to provide control over the thickness of the protective layer so that only those projections above a predetermined vertical level of the structure may be selectively treated.